High Radix On-Chip Networks at Incremental Reconfiguration Costs

Networks-on-chip (NoCs) have become increasingly widespread in recent years due to the extensive integration of many components in modern multicore processors and SoC designs. One of the fundamental tradeoffs in NoC design is the radix of its constituent routers. While high radix routers enable a richly connected and low diameter network, low radix routers provide simple and low power designs. Today, NoC designs take significant silicon area and may consume up to 30% of the entire chip power budget; thus, naïvely deploying an expensive highradix network is no longer possible. In this work, we present HiROIC 1 (HighRadixOn-chip Networks at Incremental re-Configuration Cost), to provide high-radix like performance at a cost similar to a low-radix network. HiROIC leverages the irregularity in runtime communication patterns to provide short lowlatency paths between frequently communicating nodes, while infrequently communicating pairs take longer paths. To this end, HiROIC proposes a flexible topology reconfiguration infrastructure where the abundantly available links between routers (in accordance to a highradix topology) are decoupled from scarcely available router ports (similar to a low-radix topology). The link-to-port binding is done at runtime, based on traffic patterns, using low-overhead multiplexers. HiROIC employs a statistics collection and decision-making framework to orchestrate the topology modifications that maximize performance. While our solution may require some additional and/or longer links, we observe that links are not the timing bottlenecks in contemporary router pipelines and links that are not coupled to ports could be power-gated to save power. HiROIC ensures a globally connected and deadlockfree network at all times. Our experiments on a 64-node CMP, running multi-programmed workloads, show that HiROIC reduces average network latency by 21% over an areaand powercomparable mesh NoC.